Prasert Kanthamanon. 1997. Timing analysis for hierarchical VLSI designs and high-level synthesis. , University of New South Wales;

Prasert Kanthamanon. Timing analysis for hierarchical VLSI designs and high-level synthesis. . Sydney:University of New South Wales, 1997.

Prasert Kanthamanon. (1997) Timing analysis for hierarchical VLSI designs and high-level synthesis . University of New South Wales/Sydney.